1. Field of the Invention
The present invention relates to the acquisition of binary analog signals at input of a digital integrated circuit.
The dialog between the computer and its peripherals or between several computers or again between a human operator and a computer is often carried out by means of discrete or Boolean analog electrical signals evolving around two voltage thresholds which are at a variable distance from each other, depending on the tolerated noise margins. The voltages then brought into play may be great as compared with the usually accepted voltages in the digital integration technologies most commonly used today (voltages of 5 V), thus making it necessary to obtain a voltage matching. This matching conventionally makes use of an analog interface stage with a resistive divider bridge possibly incorporating a filtering capacitor. When the voltage matching is done, it is necessary to determine the binary state of the signal by comparing its instantaneous voltage with a reference level. This is obtained by subjecting the signal coming from the analog interface stage with a level comparator made by digital technology. Since the slopes of evolution of the signals acquired by means of an analog interface stage are often very gradual as compared with the switching speeds of current digital technologies, there is a great risk of bringing about the oscillation of the digital input stage with the consequence of increased consumption, risky operation and, finally, a consequent diminishing of reliability. To overcome this, there are known ways of using Schmitt triggers instead of simple level comparators. These Schmitt triggers have a switching hysteresis with two distinct thresholds: a top threshold in the upward direction and a bottom threshold in the downward direction.
2. Description of the Prior Art
The input digital stage using Schmitt triggers is made in a cell of the digital integrated circuit. Consequently, it has the drawback wherein its electrical characteristics, hence its switching thresholds, are fixed during the characterizing of its integration cell. Now, in integration technologies, the characterizing of the cells is a costly operation which it is sought to avoid to the greatest possible extent. Thus, it is usual to define the architecture of an ASIC (Applications Specific Integrated Circuit) that is prediffused or pre-characterized on the basis of various types of pre-characterized cells established in advance and pooled in a library. The designer of an ASIC therefore, in order to make a binary analog signal discrete (i.e. draw a two-state logic signal out of it), has only one choice in a limited set of several types of Schmitt trigger input digital stages with fixed characteristics, a set often limited to two types, one using the TTL standard and the other using the CMOS standard. It sometimes happens that, in the set of Schmitt trigger input digital stages available, none is really suitable. The result of this is that, unless the costly solution of developing a specific cell is adopted, the designer of an ASIC circuit must opt for an available type of Schmitt trigger digital input stage having top and bottom switching thresholds which are not at the desired levels but are simply close to them. The digital integrated circuit obtained then shows greater sensitivity to noise or requires a more complex matching stage.
It is an aim of the present invention to combat this drawback by providing a designer of an ASIC digital integrated circuits with increased possibilities in the choice of the top and bottom switching threshold levels of an input digital stage despite the limitations dictated by the fact that there is a limited number of Schmitt trigger input digital stages pre-characterized in a library.